1. Field of the Invention
The present invention relates to a level shifter circuit for shifting a voltage level of an inputted signal, and more particularly to a level shifter circuit capable of being fabricated in a display panel having polycrystalline silicon thin film transistors and a built-in latch circuit.
2. Description of the Related Art
Flat panel display devices such as liquid crystal displays (LCDs), electro-luminescence (EL) display devices, plasma display panels (PDPs), and the like, are being used to replace cathode ray tubes (CRTs). Of the aforementioned flat panel display devices, LCDs alter transmittance of light generated by a light source using dielectric anisotropy of liquid crystals within electric fields to display pictures. EL display devices radiate phosphorus material by re-combining electrons with holes to display pictures.
All LCD and EL display devices use thin film transistors (TFTs) as switching devices within individual picture elements to provide active matrix driving systems. The semiconductor layer of TFTs typically is either amorphous silicon or polycrystalline silicon. Accordingly, TFTs may be classified as either polycrystalline silicon type TFTs or amorphous silicon type TFTs.
Display devices fabricated using amorphous silicon type TFTs have a relatively low pixel density because amorphous silicon has a relatively small charge mobility and low response speed. Moreover, use of amorphous silicon type TFTs in flat panel displays is disadvantageous because fabricating gate and data drivers out of amorphous silicon tends to be expensive and the time required to fabricate LCDs using amorphous silicon type TFTs tends to be lengthy due to their need to be manufactured separately from, and attached to a liquid crystal display panel.
Display devices fabricated using polycrystalline silicon type TFTs have a relatively high pixel density because polycrystalline silicon has a relatively high charge mobility. Moreover, use of polycrystalline silicon type TFTs in flat panel display devices is advantageous because they decrease the manufacturing cost of the gate and data drivers due to their ability to be formed with driving circuits built in the flat display panel. Accordingly, flat panel displays (e.g., LCDs, EL display devices, etc.) employing polycrystalline silicon TFTs will now be discussed in greater detail below.
FIG. 1 illustrates a schematic view of a related art liquid crystal display panel employing polycrystalline silicon TFTs.
Referring to FIG. 1, the LCD includes a liquid crystal display panel 10 having a picture display area 16, a data driver 12 for driving data lines DL of the picture display area 16, and a gate driver 14 for driving gate lines GL of the picture display are 16.
The picture display part 16 includes pixels arranged in a matrix pattern, wherein the pixels include liquid crystal cells LC to display pictures. Each liquid crystal cell LC includes a switching device such as a polycrystalline silicon type TFT arranged at a crossing of a gate line GL and a corresponding data line DL. As polycrystalline silicon has an electric charge mobility roughly 100 times greater than the electric charge mobility of amorphous silicon, liquid crystal cells in the LCD are driven in a point-sequence manner. The TFTs respond to scanning pulses applied to the gate lines GL to charge video signals (i.e., pixel signals), applied to data lines DL, into a respective liquid crystal cell LC. Thus, light transmittance characteristics of liquid crystal cells LC are controlled via the charged pixel signals.
The gate driver 14 shifts a start pulse inputted from an external timing controller (not shown) to generate a shift pulse, level-shifts the shift pulse, and applies the level shifted shift pulse to the gate line GL as a scanning pulse. Accordingly, the gate driver 14 includes a shift register for shifting the start pulse and also includes a level shifter for level shifting the shifted start pulse to for applying the level shifted pulse to the gate line GL as a scanning pulse. For example, the level shifter may shift the voltage level of a shift pulse having a swing voltage of about 10V such that it has a swing width of about 18V. Subsequently, the level shifter outputs the level shifted shift pulse as a scanning pulse.
The data driver 12 converts pixel data inputted from an external timing controller (not shown) into analog pixel signals and applies the analog pixel signals to the data lines DL. As shown in FIG. 2, the data driver 12 includes a shift register 22 for applying a sequential sampling signal, first and second latch arrays 26 and 28, respectively, for responding to a sampling signal to latch and output an inputted pixel data, and a digital to analog converter (DAC) array 32 for converting digital pixel data outputted from the second latch array 28 into analog pixel signals.
The shift register 22 sequentially shifts a source start pulse SSP inputted from the external timing controller in response to a clock signal CLK and outputs the shifted source start pulse SSP as a sampling signal. The first latch array 26 responds to a sampling signal outputted by the shift register 22 to sequentially sample and latch a predetermined number of bits of pixel data outputted from the timing controller and to output the latched pixel data. Accordingly, when ‘k’ pixel data is to be latched, the first latch array 26 includes k latches. Each of the k latches is of a size that corresponds to a bit number of pixel data (e.g., 3 bits or 6 bits). The second latch array 28 latches pixel data outputted by the first latch array 26 and outputs the latched pixel data in response to a source output enable signal SOE outputted by the timing controller. The driving voltage level of the source output enable signal SOE is level-shifted to a predetermined driving voltage level via the level shifter 30. The level-shifted driving voltage is then applied to the second latch array 28.
The DAC array 32 converts pixel data outputted by the second latch array 32 into analog pixel signals using an external gamma voltage source (not shown). The converted pixel signals are then applied to the data lines DL of the picture display area 16. The DAC array 32 converts positive or negative pixel signals in response to polarity control signals outputted by the timing controller (not shown).
In the liquid crystal display panel employing polycrystalline silicon TFTs, the gate and drivers 14 and 12, respectively, require inputted signals having a swing width greater than 10V in order to drive the picture display area 16. Accordingly, signals (e.g., control signals CLK and SSP and pixel data) applied to elements having a relatively high operation frequency (e.g., shift register 22 and first latch array 26) are directly applied from the external timing controller such that they have a swing width greater than about 10V. However, signals (e.g., source output enable signal SOE) applied to elements having a relatively low operation frequency (e.g., second latch array 28) are outputted from the external timing controller having a relatively low swing width of less than about 5V and are level-shifted via an internal level shifter 30 such that they has a swing width of greater than 10V. Accordingly, the timing controller must be fabricated using high voltage ICs to apply signals having a swing width of greater than 10V and must further be supplied with a high voltage of greater than 10V. Because of these aforementioned requirements, power consumption of the device is deleteriously increased.
In order to overcome the disadvantageous increase in power consumption, a level shifter may be built into the liquid crystal display panel to level-shift and supply high frequency input signals. For example, the following level shifter may be either included within the shift register 22 or located at the pre-stage of the first latch array 26 in the data driver 12 shown in FIG. 2. The aforementioned level shifter could level shift a sampling signal or pixel data having a frequency within several MHz range.
Referring to FIG. 3, a related art level shifter includes a first PMOS transistor MPT1 and a first NMOS transistor MNT1 having gate terminals that are commonly connected to an input voltage (VIN) line, wherein the first PMOS transistor MPT1 and a first NMOS transistor MNT1 are connected in series between a first power supply (VDD) input line and a third power supply (VSS2) input line; a second PMOS transistor MPT2 and a second NMOS transistor MNT2 having gate terminals that are commonly connected to a first node N1 located between the first PMOS transistor MPT1 and the first NMOS transistor MNT1, wherein the second PMOS transistor MPT2 and a second NMOS transistor MNT2 are connected in series between the first power supply (VDD) input line and the third power supply (VSS2) input line; a third PMOS transistor MPT3 having a gate terminal connected to a second node N2 located between the second PMOS transistor MPT2 and the second NMOS transistor MNT2, wherein the third PMOS transistor MPT3 is connected between the first power supply (VDD) input line and a third node N3; a third NMOS transistor MNT3 having a gate terminal connected to a fourth node N4 as an output node, wherein the third NMOS transistor MNT3 is connected between the third node N3 and a second power supply (VSS1) input line; a fourth PMOS transistor MPT4 having a gate terminal connected to the first node N1, wherein the fourth PMOS transistor MPT4 is connected between the first power supply (VDD) input line and the fourth node N4; and a fourth NMOS transistor MNT4 having a gate terminal connected to the third node N3, wherein the fourth NMOS transistor MNT4 is connected between the fourth node N4 and the second power supply (VSS1) input line. The level shifter shown in FIG. 3 further includes two inverters INV1 and INV2 connected in series to the fourth node N4. Inverters INV1 and INV2 are commonly connected to the first and second power supply VDD and VSS1.
The aforementioned level shifter circuit outputs an output pulse voltage having a swing width of −10V to 10V, assuming the pulse voltage swings +10V with respect to the first power supply VDD, −10V with respect to the second power supply VSS1, −4V with respect to the third power supply VSS2, and 0V to +5V with respect to an input voltage.
When a first low-level voltage of 0V is inputted to the input voltage (VIN) line, the first PMOS transistor MPT1 is turned on and charges a first high-level voltage of 10V, supplied from the first power supply VDD, into the first node N1. The first high-level voltage of 10V, charged into the first node N1, turns on the second NMOS transistor MNT2 which, in turn, charges a second low-level voltage of −4V, supplied from the third power supply VSS2, into the second node N2. The second low-level voltage of −4V, charged into the second node N2, turns on the third PMOS transistor MPT3 which, in turn, charges a second high level voltage of 10V, supplied from the first power supply VDD, into the third node N3. The second high-level voltage of 10V, charged into the third node N3, turns on the fourth NMOS transistor MNT4 which, in turn, charges a third low-level voltage of −10V, supplied from the second power supply VSS1, into the fourth node N4 as an output node. The second high-level voltage of 10V, charged into the first node N1, turns off the fourth PMOS transistor MPT4. Accordingly, the third low-level voltage of −10V, charged into the fourth node N4, is applied as an output voltage VOUT via the first and second inverters INV1 and INV2. As a result, the first low-level voltage of 0V, inputted as the input voltage (VIN), is level-shifted into the third low-level voltage of −10V.
When a first high-level voltage of 5V is inputted as an input voltage VIN, the first NMOS transistor MNT1 is turned on and charges a first low-level voltage of −4V, supplied from the third power supply VSS2, into the first node N1. The first low-level voltage of −4V, charged into the first node N1, allows the second and fourth PMOS transistors MPT2 and MPT4 to be turned on to charge a second high-level voltage of 10V, supplied from the first power supply VDD, into the second and fourth nodes N2 and N4. The second high-level voltage of 10V charged at the second node N2 allows the third PMOS transistor MPT3 to be turned off while the second high-level voltage of 10V charged in the fourth node N4 allows the third NMOS transistor MNT3 to be turned on. Accordingly, a second low-level voltage of −10V is applied to the third node N3 to turn off the fourth NMOS transistor MNT4. Thus, the second high-level voltage of 10V, charged into the fourth node N4, is applied as the output voltage VOUT via the first and second inverters INV1 and INV2. As a result, the first high-level voltage of 5V, inputted as an input voltage VIN, is level-shifted into the second high-level voltage of 10V.
Referring to FIG. 3, the level shifter circuit level-shifts an inputted voltage VIN having a swing width of 0V˜5V into an output voltage VOUT having a swing width of −10V˜10V and outputs the output voltage VOUT. Use of the level shifter circuit shown in FIG. 3, however, is disadvantageous in that a third power supply (i.e., VSS2) is required whereas other level shifter circuits do not require any such third power supply. Further, the MOS transistors MNT and MPT in the level shifter shown in FIG. 3 are made of polycrystalline silicon. Fabricating transistors using polycrystalline silicon is difficult. Still further, when threshold voltages of various MOS transistors in a circuit become different, the level shifter circuit may not work properly. For example, as the threshold voltage of the MOS transistors MNT and MPT increases, the amount of turn-on current decreases and the output voltage VOUT is reduced.
Generally, threshold voltages of polycrystalline silicon type thin film transistors are much greater than those of amorphous silicon type thin film transistors because threshold voltages of polycrystalline silicon type TFTs are influenced by the electric charge mobility of the polycrystalline silicon material. The electric charge mobility of the polycrystalline silicon is influenced by the size of the grain boundaries produced in the TFT when polycrystalline silicon crystallizes. Typically, grain boundaries of crystallized polycrystalline silicon vary in size depending on the location on the substrate where the polycrystalline crystallizes. Accordingly, thin film transistors MNT and MPT, while concurrently fabricated on a single substrate, will have grain,boundaries of varying sizes and the threshold voltages of the various MNT and MPT TFTs will vary due to their location on the substrate where they were fabricated. Since the threshold voltages of the various MNT and MPT TFTs vary, threshold voltages of the level shifter circuits are not uniform. Level shifter circuits such as those illustrated in FIG. 3 cannot compensate for changes in the threshold voltage and the level shifter circuit deteriorates in reliability and the output voltage is reduced.
FIG. 4 illustrates a level shifter circuit capable of being built within a liquid crystal display panel employing polycrystalline silicon.
Referring to FIG. 4, the related art level shifter circuit includes a first PMOS transistor MPT1 having gate and source terminals commonly connected to the first node N1 and having a drain terminal connected to the supply line of the first power supply VDD; a first NMOS transistor MNT1 having gate and drain terminals commonly connected to the first node N1 and having a source terminal connected to the supply line of the second power supply VSS; a second PMOS transistor MPT2 having gate terminal connected to the first node N1 and connected between the supply line of the first power supply VDD and the second node N2 (i.e., the output node); a second NMOS transistor MNT2 having a gate terminal connected to the first node N1 and being connected between the second node N2 and the input line. The level shifter circuit shown in FIG. 4 further includes two inverters INV1 and INV2 connected in series with the second node N2. Inverters INV1 and INV2 are commonly connected to the first and second power supply VDD and VSS.
The first PMOS transistor MPT1 and the first NMOS transistor MNT1, connected in series between the supply line of the first power supply VDD and the supply line of the second power supply VSS, are always maintained in a turned-on state and act as a voltage distributor.
When a low-level voltage of 0V is inputted as the input voltage VIN, the second NMOS transistor MNT2 is turned on and the second PMOS transistor MPT2 is turned off. Accordingly, the low-level voltage of 0V is charged in the output node N2 and is outputted as the output voltage VOUT via the first and second inverter INV1 and INV2.
When a high-level voltage of 5V is inputted as the input voltage VIN, the second NMOS transistor MNT2 is turned off and the second PMOS transistor MPT2 is turned on. Accordingly, the high-level voltage from the first power supply VDD is charged in the output node N2 and is outputted to the output voltage VOUT via the first and second inverter INV1 and INV2.
Level shifter circuits such as those illustrated in FIG. 4 do not need any additional power supply and they require a relatively fewer number of MOS transistors as level shifter circuits such those illustrated in FIG. 3. However, the level shifting range extremely limited and the operable frequency of the level shifter drops remarkably since the low-level of the level-shifted output voltage VOUT is fixed by the low-level voltage of the input voltage VIN. Further, and for reasons explained above with reference to FIG. 3, there is no way to compensate for a change in the threshold voltage of the MOS transistors. Accordingly, the reliability of the level shifter circuit may be deteriorated such that the output voltage VOUT is reduced. Further, in level shifters such as those illustrated in FIG. 4, the first PMOS and first NMOS transistors MPT1 and MNT1 are maintained in a turned-on state at all times. Accordingly, a current path is formed between the first power supply VDD and the second power supply VSS. When the current path is so formed, power dissipation of the device becomes excessively large due to generation of a static current.
Moreover, when the first latch array 26 shown in FIG. 2 is provided at a preceding stage, the inputted pixel data are level-shifted by one bit and the number of first latch arrays required equals the total number of the bits of pixel data. Accordingly, in order to build level shifters for level-shifting pixel data in liquid crystal display panels, the number of the bits of pixel data needs to be very small. However, the number of the bits of pixel data is proportional to the number of the level shifters. As a result, the aforementioned related art level shifter cannot be practically applied to display panels capable of displaying images at with high resolution and high colorization and having a large number of pixels.
FIG. 5 illustrates a circuit with respect to a 1-bit latch included within the first latch array 26 shown in FIG. 2.
Referring to FIG. 5, the 1-bit latch includes a first PMOS transistor MPT1 and a first NMOS transistor MNT1 having gate terminals commonly connected to the supply line of the input voltage VIN and being connected between the supply line of the first power supply VDD and the supply line of the second power supply VSS; a second NMOS transistor MNT2 having a gate terminal connected to the supply line of a sampling pulse SP and also connected between the first NMOS transistor MNT1 and the supply line of the second power supply VSS; a second PMOS transistor MPT2 having a gate terminal connected to the supply line of an inverted sampling pulse SPB and also being connected between the supply line of the first power supply VDD and the first PMOS transistor MPT1; a first inverter INV1 for inverting the voltage of the first node N1, located between the first PMOS transistor MPT1 and the first NMOS transistor MNT1, and for supplying the voltage to the output voltage VOUT; and a second inverter INV2 for inverting the output voltage VOUT and returning the inverted output voltage back to the first node N1.
When a sampling pulse SP represents a high state and an inverted sampling pulse SPB represents a low state and are both outputted from the shift register 22 shown in FIG. 2, and when an input voltage VIN representing a low state is inputted, the first and second PMOS transistors MPT1 and MPT2 are turned on and the first node N1 is supplied with a high-level voltage of the first power supply VDD. Accordingly, the first inverter INV1 inverts the high-level voltage of the first node N1 and outputs the output voltage VOUT representing a low state (i.e., a low-level voltage). When the input voltage VIN representing a high state is inputted, the first and second NMOS transistors MNT1 and MNT2 are turned on so the first node N1 is supplied with a low-level voltage of the second power supply VSS. Accordingly, the first inverter INV1 inverts the low-level voltage of the first node N1 and outputs the output voltage VOUT representing a high state. Moreover, the second inverter INV2 is turned off by the sampling pulse representing a high state and the inverted sampling pulse SPB representing a low state.
When the sampling pulse SP represents a low state and the inverted sampling pulse SPB represents a high state and when both are outputted from the shift register 22 shown in FIG. 2, the second PMOS transistor MPT2 and the second NMOS transistor MNT2 are turned off while the second inverter INV2 is turned on. Accordingly, the first and second inverters INV1 and INV2 invert the voltage of the preceding state in the first node N1 regardless of the input voltage VIN and subsequently apply the inverted voltage to the output voltage VOUT. Subsequently, the output voltage VOUT is inverted and returned to the first node N1, thereby maintaining the output voltage VOUT at the preceding state.
Level shifters and latches such as those described above include a relatively large number of transistors. Accordingly, when the level shifters such as those illustrated with reference to FIG. 3 or 4 are added to the pre-stage or post-stage of latches such as those illustrated with reference to FIG. 5, the number of transistors increases along with the circuit area. Accordingly, fabricating data drivers by combining the aforementioned level shifter and latch is not practical in fabricating high resolution display panels capable of attaining high levels of colorization that require increasing bits of pixel data.